- US Commerce Secretary says US to produce 20% of leading-edge chips by 2030. We project US to make at least 10% of sub-10nm chips by 2030.
- Intel, Samsung and TSMC have transformed the US into a 2nm process battleground with more than half of the CHIP Act direct subsidies in their coffers.
- The downside risk of the overseas expansion will be higher wafer prices.
The disruptions caused by the Covid-19 pandemic spurred the US to focus on revitalizing its semiconductor industry, while global trade tensions prompted it to reevaluate its reliance on Asian manufacturing. With a noticeable decline in its global semiconductor manufacturing share, the US is now advocating for domestic fabrication facilities. Globally, over 70% of foundry market revenues stem from Asia, with the US contributing less than 10%.
In August 2022, US President Joe Biden signed the CHIPS and Science Act, allocating $280 billion to advance semiconductor research and manufacturing in the US. Out of this sum, $52.7 billion was earmarked for chip manufacturing subsidies and tax credits, with an additional $13 billion for research and training, aimed at fortifying US supply chains and ensuring the success of the country’s semiconductor industry. US Secretary of Commerce Gina Raimondo aims for the US to produce 20% of the world’s leading-edge logic chips by 2030. With significant US investments, we project at least 10% of sub-10nm chips will be made domestically by 2030.
Global Leading Foundries Receive Around 55% of US Subsidies
In a recent series of multi-billion-dollar grants, Intel, TSMC and Samsung collectively received over half of the $39 billion CHIPS Act incentives. The Act has initiated numerous projects aimed at boosting manufacturing capacity in the US, especially for advanced nodes.
Intel is set to receive up to $8.5 billion in direct funding to propel its domestic semiconductor projects. The company also stands to benefit from a US investment tax credit of up to 25% on more than $100 billion in qualified investments.
TSMC touted agreements with the US government to secure $6.6 billion in direct funding. The agreement also proposes to provide TSMC with as much as $5 billion in loans and up to 25% tax credits for its $65 billion capital expenditure in Arizona.
Samsung was granted a $6.4 billion subsidy for its $45 billion chip investment in Taylor, Texas where it is building a 4nm EUV manufacturing facility. The plant is set to begin mass production in 2025.
Foundry Giants Compete to Produce Next-gen Cutting-edge Chips
As funds flow into US coffers, we expect a showdown among top advanced-node chipmakers, Intel, Samsung and TSMC, to turn the US into the battleground for 2nm processes. Recent updates reveal advancements in the advanced nodes of these companies’ US plants.
Intel’s ambitious plan, dubbed 5N4Y, targets the release of five nodes within four years, with the 18A process slated to lead by 2025. Recent milestones include the completion of the first 18A product (Clearwater Forest), with volume ramp-up expected by 2025. Furthermore, Intel has enhanced its roadmap to feature the more advanced 14A in its leading-edge node lineup.
TSMC’s first Arizona plant (N4) is slated for production in H1 2025, with plans for a second plant to produce 2nm chips alongside the previously announced 3nm. This second plant, expected to launch in 2028, could increase TSMC’s capacity to 50,000 wafers per month. Notably, TSMC aims to serve prominent US customers like Apple, NVIDIA, AMD and Qualcomm with its advanced process capacity in the US. Additionally, the availability of 2nm chips in the US could bolster TSMC’s market share against Intel’s 18A process.
Samsung is constructing a 4nm EUV manufacturing facility in Taylor, Texas, set to commence mass production in 2025. Initially, only a limited volume of equipment setup is expected, capable of producing 5,000 12-inch wafers per month by H2 2024.
Source: Counterpoint Research
Overseas Expansion Risks Could Lead to Higher Wafer Prices
In the realm of more sophisticated technology nodes, greater quantities of materials will be required for additional layers and process steps in wafer production. Historically, we have observed a 5%-15% uptick in the total number of mask layers. Additionally, other cost drivers such as maintenance and labor expenses are anticipated to emerge.
These factors will inevitably raise the overall cost structure. We project that inflation in fab construction costs will continue to outpace broader inflation levels, at least until 2030. This is primarily due to the absence of a sustained volume of new fab buildouts in the US.
